As promised here is a technical overview of the Dual Peribus High Speed Serial Interface (otherwise known as WEETABIX for reasons that at present escape me) as used in the Bloodhound Launch Control Post.
The Dual Peribus High Speed Serial Interface provides a programmable parallel/serial communications interface between an Argus 700 Peribus and two full duplex high speed (RS422) serial lines.
Z80 Interface Registers
These registers contain information on the state of the FIFO buffers, transfer status, Z80 status and the status of the Enhanced Programmable Communications Interface (EPC)I status register.
TX and RX First-In-First-Out (FIFO) Buffers
Each of the two channels has a 512 byte FIFO buffer for both transmitting and receiving data (ie. there are four of these buffers per card). These buffers are interfaced directly to the PERIBUS so as to facilitate fast data transfers. The transmission buffers are loaded via the PERIBUS and can be accessed at up to a 140mS write cycle. Once there is data present in the FIFO then transfer to the EPCI and serial conversion can be started at once.
If the EPCI that is to be used, is being accessed by·the Z80 system, then the transfer from FIFO to EPCI is held up until the Z80 system has finished. Whilst the FIFO is waiting to transfer data its data lines are in the high impedance state.
The receiver buffers are interfaced directly to the PERIBUS and are filled by the EPCI. Onnce again, if the Z80 system is accessing the EPCI then no transfers from the EPCI to the FIFO are implemented. The operation of transfers between the FIFOs and the EPCIs is controlled by a Programmable Array Logic (PAL) device.
The FIFOs are reset by “software pulsing” via the PERIBUS. The status of the FIFOs (empty or full) is also available to the PERIBUS via a register.
The PERIBUS signal STATUS is used to indicate that a status read or write control is being performed at a particular address. This facility is used as follows:
1. STATUS read on TX lines:
DIB1′ TX FIFO empty
DIB2′ State of CTS Input to EPCI
DIB3′ Transfer complete
DIB4′ Transfer error
DIBS’ Not used
OIB6′ Not used
DIB7 ‘ TX FIFO full
OIB8′ Logic 0
DIB24′ TX FIFO full
2. STATUS read on RX address:
DIB1’ State of RXD input to EPCI
OIB2 ‘ Data carrier fail*
DIB3′ Framing error*
OIB4′ Pari t y error*
OIBS’ Not used
OIB6′ Overrun error*
DIB7 ‘ RX buff er empty
OIB8’ Logic 0
DIB24 ‘ RX buffer empty
OIBN lines are high when appropriate function is true.
* Signifies that these signals are derived from the External Status Register.
3. Status write (ie. control) on TX address:
OOBl Clear RX FIFO
00B2 Clear TX FIFO
00B3 Reset EPCI
00B4 Reset External Status Register
OOBS Select interface standard RS422A (1) or RS423A (0)
00B6 Select card TX clock 983KHz (1) or 491KHz (0)
00B7 Select TR (1) or BUSY (0)
00B8 Select card TXCLK (1) or ST (0)
OOBN lines are low when appropriate function is true.
Bits 1, 2, 3 and 4 will be pulsed by software bits. 5,6,7 and 8 are latched by card.
4. Status write (ie. control) on RX1 address:
DOB8 is pulsed by software to reset the Z80.
The main function of the Z80 system (for each channel) is as follows:
1. Set-up of the EPCI by loading the appropriate registers using host-supplied data, this includes selection of communications format, baudrate, etc.
2. Read EPCI registers on request and return data to the HOST via the PERIBUS.
3. Control enabling/disabling of the EPCI external clock sources in accordance with the proposed setting of MODE REGISTER 2 bits 24-27 (eg. if TXC pin is to be programmed as an output. any gates driving it must be set to high impedance).
4. Handle data transfers to and/or from the EPCI having disabled the EPCI port of the appropriate FIFO.
Enhanced Programmable Communications Interface
A Signetics SC266lB Enhanced Programmable Communications Interface (EPCI) is used for each of the two channels. This is a device which is programmable for operation in a variety of different modes. Programming is done via a microprocessor type interface and a minimum configuration Z80 system is used to control the operation of both EPCIs.
The interface standard is RS449 with electrical specification RS422 (differential drivers/receivers). The interchange circuits SG. SD. RD. TT. ST. RT. RS. CS. RR. TR. and DM are implemented. In addition to these signals an RX buffer full (BUSY) output (single-ended and differential) is provided. The connectors specified in RS499 are not relevant to this card since all signals are interfaced via the edge connecto
The serial/parallel interface is a Signetics SC2661B EPCI, programming of this device is done via the Z80 with data from the PERIBUS. A DIL switch sets the baud rate and an LED
lights to indicate communications between the Z80 and the EPCI.